This invention relates to an interconnection medium for electrically connecting electronic components.
With the increasing complexity of systems employing semiconductor integrated circuits has come a corresponding complexity of the interconnection medium for electrically coupling separate ICs. This medium has traditionally taken the form of printed circuit boards. The technology, while adequate for present needs, may be insufficient for future systems requiring high speed operation and high density conductive patterns. Workers in the art, therefore, have been developing advance packaging designs including wafer scale integration where the interconnection medium is a silicon wafer with conductors formed according to integrated circuit processing techniques.
Whichever interconnection approach is used, but especially in the wafer scale technology, the presence of faults in the conductors will become increasingly significant. A single fault, whether an open or short, can render the interconnection medium unusable and yields, therefore, can be unacceptably low for complex circuits.
Proposals have been made for dealing with the problem of defective chips or memory cells by providing additional chips or cells which would be connected in the final circuit in the event of a defect in one or more of the original elements. (See, e.g. U.S. Pat. No. 3,940,740) issued to Coontz and U.S. Pat. No. 4,354,217 issued to Mahon). However, to the best of applicant's knowledge, workers in the art have not addressed the problem of defects in the interconnection medium which connects the various circuit chips together.
It is, therefore, an object of the invention to provide an interconnection medium which is tolerant of defects in the conductors making up the interconnection scheme.